Parallelinserialout

Parallelinserialout, often referred to as parallel-in serial-out (PISO), describes a digital data path that converts a parallel data word into a serial bit stream on a single output line. It is the counterpart to serial-in parallel-out (SIPO) and is commonly implemented using shift-register architectures. A PISO device typically includes a set of parallel data inputs (D0 through Dn), a parallel load input (PL) to capture the bus, a clock input to drive shifting, and a serial data output (Qser). Some variants also provide a clock enable (CE) and a reset.

Operation involves two phases. First, a parallel load is performed by asserting PL, which transfers the present values on the parallel inputs into the internal shift register. After loading, subsequent clock pulses shift the register contents toward the serial output, emitting one bit per clock on Qser. The width of the parallel bus defines the number of bits in the word (for example, 8, 16, or 32). The serial order of the output follows the device’s predefined shift direction.

Common implementations and use cases include the 8-bit 74HC165 family, a widely used PISO device. PISO registers are employed to read multiple parallel sensors or switches with a single microcontroller input, to serialize data for transmission over a single line, and to extend I/O via daisy chaining. They also appear in applications such as LED matrix driving and peripheral interfacing where minimizing input pins is advantageous.

Considerations for designers include maximum shifting speed, data setup and hold times, propagation delays, and the availability of features like inverted load or asynchronous reset. Many PISO devices can be chained to handle larger word widths.