InterruptController

An interrupt controller, sometimes written as interruptcontroller in documentation, is a hardware block in a computer system that mediates interrupt requests (IRQs) from peripherals or internal components, choosing which interrupt to service and delivering it to the processor. Its core responsibilities include prioritizing multiple simultaneous requests, masking or unmasking sources, and signaling the processor with an interrupt vector or ID. It may also implement end-of-interrupt semantics to allow the system to resume normal operation.

Most systems separate interrupt controllers into a local controller tied to each CPU core and an I/O controller that collects external device requests. In older architectures a single programmable interrupt controller (PIC) managed a small fixed set of IRQ lines. Modern designs use scalable interrupt controllers such as the Advanced Programmable Interrupt Controller (APIC) family, consisting of a local APIC per core and an I/O APIC to route external interrupts. APICs support fine-grained priority, software-generated interrupts, masking, and interrupt remapping for security and virtualization. They also provide mechanisms to distribute interrupts across cores and handle nested or preemptive servicing.

In ARM systems, similar roles are fulfilled by the Generic Interrupt Controller (GIC), while Cortex-M devices use the Nested Vectored Interrupt Controller (NVIC). In virtualized environments, interrupt controllers may present virtualized interfaces to guest operating systems, and support features like MSI (message-signaled interrupts) to improve performance.

A well-designed interrupt controller enables lower latency interrupt handling, reduces interrupt storms, and improves overall throughput by efficiently managing interrupt distribution and processing.