CHERIaware

CHERIaware is a software platform developed by ARM and the University of Cambridge. It is designed to explore and demonstrate the CHERI (Capability Hardware Enhanced RISC Instructions) architecture. CHERI is a security-focused extension to the RISC-V instruction set architecture that aims to prevent common software vulnerabilities like buffer overflows and memory corruption. CHERIaware provides a simulated environment where developers and researchers can experiment with CHERI's capabilities without requiring specialized hardware.

The platform typically includes a CHERI-enabled processor simulator, a toolchain (compiler, assembler, linker) that supports CHERI instructions, and example programs. These examples showcase how CHERI's capabilities, such as fine-grained memory protection and provenance tracking, can be leveraged to build more secure software. CHERIaware is an important resource for understanding the potential of capability-based security models in modern computing. It allows for the testing of new security paradigms and the development of software that can take advantage of hardware-level security features. The project contributes to the broader effort of improving software security by addressing fundamental memory safety issues at the hardware level.