4N1

4n1, short for a four-to-one multiplexer, is a combinational logic device used to route one of four input signals to a single output under control of two select lines. In electronics literature and schematics it is often labeled as 4N1 or 4:1 MUX. A 4n1 can be realized in several ways, including gate-level implementations or cascaded multiplexers.

In operation, the inputs are typically denoted D0, D1, D2, and D3, with select lines S0 and S1. The output Y follows a fixed mapping: Y = D0 when S1S0 = 00, Y = D1 when S1S0 = 01, Y = D2 when S1S0 = 10, and Y = D3 when S1S0 = 11. This makes the circuit a data selector: it forwards exactly one of the four data inputs to the output according to the binary value of the select lines.

Common implementation methods include using two 2:1 multiplexers in a cascaded arrangement (the first stage selects between D0 and D1, and between D2 and D3, followed by a second-stage multiplexer to choose between the two results), or an AND-OR network that generates the output as a sum of minterms gated by the select signals. Many integrated circuit families include dedicated 4:1 multiplexers as single-gate solutions.

Applications for 4n1 devices include data routing in digital systems, memory and bus architectures, arithmetic logic units, instruction decoding, and general-purpose data path selection where one of several inputs must be directed to a common output based on control logic.