setassociativ

Set-associative caches are a type of CPU cache organization that sits between direct-mapped and fully associative caches. The cache is divided into a number of sets, each containing a fixed number of lines called ways. A memory block can be placed in any line within its mapped set, with the set determined by part of the memory address. A tag stored with each line is used to verify the identity of the block during a lookup.

Addressing in a set-associative cache uses an offset, an index (the set number), and a tag. The index selects the set, and the tag is compared against the stored tags in all lines of that set. A match in any line yields a cache hit; otherwise, the access misses and the block must be fetched from a higher level of memory.

The level of associativity is the number of lines per set (for example, 2-way, 4-way, 8-way). Higher associativity reduces conflict misses by allowing more blocks to reside in the same region of the cache, but it also increases hardware complexity, access time, and power consumption. Direct-mapped caches are a special case with one line per set, while fully associative caches have a single set containing all lines.

Replacement policies determine which line to evict when a set is full. Common choices include least recently used (LRU), pseudo-LRU, FIFO, and random replacement. In practice, implementations balance associativity, size, and speed to optimize hit rate and latency.

Set-associative caches are widely used in modern CPUs for L1, L2, and L3 levels. They also play a role in coherence protocols (such as MESI) to maintain consistency across cores. The exact configuration varies by architecture, but the core idea remains: map memory blocks to sets and search within the set for the best match.