gatespänning

Gatespänning, or gate voltage in English, is the electrical potential difference applied to the gate terminal of a field‑effect transistor (FET) to control its conductivity. It is typically measured relative to the source and determines whether a channel forms and how strongly it conducts.

In MOSFETs (metal-oxide-semiconductor FETs) the gate is electrically insulated from the channel by a thin oxide layer. Ideally no direct current flows into the gate. The gate voltage modulates the carrier density under the oxide, creating or suppressing a conductive channel. A threshold voltage, Vgs(th), marks the transition from off to on. Devices are described as enhancement‑mode (conducting when Vgs exceeds the threshold) or depletion‑mode (conducting with little or no gate bias, reduced by applying Vgs). For NMOS devices, positive Vgs promotes conduction; for PMOS, negative Vgs does.

In JFETs (junction FETs) the gate forms a PN junction with the channel. The gate current is typically small, and applying reverse bias to the gate narrows the conducting channel, reducing current. At zero gate bias, many JFETs conduct (depletion‑mode behavior) and can be pinched off with increased reverse bias.

Practical considerations include safe operating ranges defined by device datasheets (maximum Vgs), gate leakage currents, and the influence of gate capacitance on switching speed (Cgs, Cgd). Exceeding the maximum gate voltage can cause dielectric breakdown and permanent device damage. Gatespänning is therefore a fundamental control variable in both digital logic and analog transistor circuits.