cachelines

Cache lines are the atomic units of data moved between a processor's cache and main memory. A cache line represents a contiguous block of memory, typically 32 to 256 bytes, that the cache can store and transfer in a single operation. When the processor executes a memory access, the cache checks if the required bytes reside within a line already loaded; if not, the line containing the requested address is fetched from a lower level of the memory hierarchy and stored in the cache.

Each cache line includes the data block plus metadata. The data field holds the bytes of memory. The tag identifies the memory address range stored in the line. A valid bit indicates if the line contains useful data, and a dirty bit marks whether the data has been modified since it was loaded (in write-back caches). The address is split into offset, index, and tag: offset selects a byte within the line, index selects a cache set, and tag distinguishes different blocks that map to the same set.

Caches are organized into levels (L1, L2, L3) and may be set-associative. A line maps to one of several sets; a set contains multiple lines (ways). The cache may be inclusive, exclusive, or non-inclusive between levels, and coherence protocols (e.g., MESI) ensure correctness in multi-core systems.

Impact on performance: larger line sizes can improve spatial locality by bringing more data per miss but may increase eviction of useful data and worsen working-set efficiency; smaller lines reduce pollution but may increase miss rates for streaming data. False sharing occurs when threads write to different variables within the same cache line, creating unnecessary inter-thread traffic and invalidations.