TLBmiss

TLBmiss refers to the condition in a computer's memory management unit (MMU) where a virtual address translation is not found in the translation lookaside buffer (TLB). The TLB is a small, fast cache that stores recently used virtual-to-physical address mappings to speed up address translation in systems using virtual memory. When a processor accesses memory using a virtual address, the MMU checks the TLB for the translation. A hit yields a physical address quickly; a miss requires a page table walk to obtain the translation from the process's page tables in memory, possibly walking multiple levels. The resulting translation is loaded into the TLB, and the memory access is re-issued.

If the page table entry indicates the page is not present in physical memory, a page fault occurs; the operating system then loads the page from disk into RAM, updates page tables, and restarts the instruction. The page fault is a separate mechanism from the TLB miss, but it is a common cause of extended latency following a miss.

Impact and optimization considerations: TLB misses are a major factor in virtual memory latency. Miss penalties depend on memory latency, page table depth, and TLB size. Techniques to reduce misses include using larger page sizes (huge pages), TLB prefetching, and architectures with multi-level or hashed TLBs. Improving locality of memory access and careful memory allocation strategies across processes can also reduce miss rate. Some systems employ address space identifiers and coordinated TLB maintenance to manage coherence across cores.