Speicherzugriffsgeschwindigkeit

Speicherzugriff, or memory access, is the process by which a processor reads from or writes to memory. It covers interactions across the memory hierarchy, from CPU registers and L1/L2/L3 caches to main memory and, ultimately, to secondary storage. The performance of a memory access depends on latency (the time to complete a single access) and bandwidth (the amount of data transferred per unit time). Caches reduce average latency by exploiting temporal and spatial locality, while slower main memory and storage impose higher delays.

In modern systems, virtual memory abstracts physical memory through an address translation unit (MMU). Processes work with virtual addresses that are translated to physical addresses by page tables and a translation lookaside buffer (TLB). When a translation is missing, a page fault occurs, potentially loading data from disk and increasing latency. Memory protection mechanisms also enforce isolation between processes and user-space and kernel-space boundaries.

Access patterns matter for performance. Locality of reference, prefetching, and proper data alignment influence cache efficiency. In multi-core or multi-processor systems, cache coherence protocols (for example MESI) ensure that copies of data remain consistent across caches. Memory bandwidth must compete among cores and devices, and memory controllers coordinate requests over the memory bus.

Security and protection are integral to memory access: memory protection units enforce isolation, and virtual memory decouples the address space of each process from others. Memory access remains a central consideration in software design, influencing data structures, algorithms, and programming language implementations through its impact on latency and throughput.