Oddr
ODDR is a digital logic primitive used in some field-programmable gate arrays (FPGAs) to implement double-data-rate (DDR) outputs on a single data line. It accepts two data inputs, typically labeled D1 and D2, and a clock input. The output Q follows D1 on the rising edge of the clock and D2 on the falling edge, enabling data to be driven at twice the clock rate when compared with single-edge registers. Many implementations also include a clock enable input (CE) and, in some variants, asynchronous set (S) and reset (R) controls.
In operation, the ODDR drives the output with D1 during the alternating phase corresponding to the clock’s
Applications for ODDR include high-speed memory interfaces, video and graphics pipelines, and other DDR-style point-to-point or