Oddr

ODDR is a digital logic primitive used in some field-programmable gate arrays (FPGAs) to implement double-data-rate (DDR) outputs on a single data line. It accepts two data inputs, typically labeled D1 and D2, and a clock input. The output Q follows D1 on the rising edge of the clock and D2 on the falling edge, enabling data to be driven at twice the clock rate when compared with single-edge registers. Many implementations also include a clock enable input (CE) and, in some variants, asynchronous set (S) and reset (R) controls.

In operation, the ODDR drives the output with D1 during the alternating phase corresponding to the clock’s rising edge and with D2 during the phase corresponding to the falling edge. This DDR behavior is essential for high-speed interfaces that rely on data changes on both edges of the clock. The primitive is typically used in conjunction with output buffers and precise timing constraints to meet required drive strength, skew, and setup/hold specifications. Variants and naming conventions vary by FPGA family; common examples include ODDR, ODDR2, and ODDR3 in different generations or toolchains.

Applications for ODDR include high-speed memory interfaces, video and graphics pipelines, and other DDR-style point-to-point or bus-oriented connections where doubling the effective data rate on a single line is advantageous. Designers select D1, D2, CE, and timing controls to align with the target protocol and overall system timing. While ODDR provides DDR output capability, it is one component in a broader design that also requires appropriate buffers, constraints, and peripheral interfaces.