Cr0

CR0 is a control register used by x86 processors to configure core operating modes and certain memory and caching features. It is a privileged register, meaning it can only be read or written from authorized kernel or supervisor mode; user-space code cannot modify CR0 directly in protected environments. The bits within CR0 control fundamental behaviors such as whether the processor is in real or protected mode, whether virtual memory paging is enabled, and how caches and memory protection behave.

Key functions controlled by CR0 include: enabling protected mode, enabling paging (which activates the processor’s virtual memory system), and enabling write protection of read-only pages when running in supervisor mode. CR0 also contains bits that influence the x87 floating-point unit behavior, such as emulation, monitoring, and task-switch handling, as well as flags that affect alignment checks and cache policy. While the exact bit positions can vary slightly between processor generations, the categories of control they provide are consistent across IA-32 and IA-32e (x86-64) architectures.

In practice, CR0 plays a central role during system boot and during mode transitions. Early in boot, an operating system sets CR0 to switch from real mode to protected mode; later, the OS toggles CR0.PG to enable or disable paging as virtual memory is brought online. The WP bit is commonly used to enforce kernel read/write protections on memory, while CD and NW control caching behavior for performance tuning or debugging. In 64-bit mode, paging remains essential, and many CR0 bits are reserved or implemented with architecture-specific nuances, but the fundamental purpose—to configure mode, memory protection, and caching—remains unchanged.