CPUcaches

CPU caches are small, fast storage near a central processing unit that hold copies of recently used data and instructions. They reduce latency by exploiting temporal and spatial locality, allowing the processor to avoid frequent accesses to slower main memory. Modern processors implement several cache levels, often with separate L1 data and L1 instruction caches, a larger L2, and a shared or private L3 cache. Some also include an L4 level.

Caches organize memory in lines, typically 64 bytes, and in a set-associative structure. A request checks the cache hierarchy; hits return data quickly, misses fetch from a lower level and possibly evict an existing line. Writes are usually performed with write-back and write-allocate, though write-through and other schemes exist.

In multi-core systems, caches must stay coherent. Protocols like MESI track line states to ensure visibility of writes; coherence traffic can incur latency. Poor cache behavior, such as false sharing, can degrade performance even if there is abundant cache space.

Cache performance depends on size, associativity, and latency, as well as software locality. Compilers and developers can improve performance by aligning data, improving spatial locality, and avoiding contention. Designers balance cache size, speed, area, and power to fit targeted workloads.