covergroups

Covergroups are a SystemVerilog language construct used to collect functional coverage data during simulation. They group together sampling points, known as coverpoints, and optional cross-coverage to measure how signals and conditions in the design are exercised. The primary purpose of a covergroup is to quantify verification completeness by reporting which functional scenarios have been encountered and which have not.

A covergroup contains one or more coverpoints and can include cross constructs. A coverpoint defines a sampling point, typically a signal or expression, and associates bins that categorize observed values. Bins may represent value ranges, discrete values, or enumerated states. A cross defines coverage for the combination of two or more coverpoints, enabling measurement of correlations and interactions between signals rather than their independent occurrences.

Covergroups are instantiated in the testbench and can be sampled in two ways. They can be triggered to sample automatically on a specified event, such as a clock edge, or sampled manually by calling a sample() method from stimulus code. The sampling process records observations into the defined bins and crosses, building a coverage database that tools report as coverage metrics. The resulting coverage data is used to guide test generation and assess coverage goals, identify gaps, and drive regression planning.

SystemVerilog covergroups are widely used for functional coverage in verification environments, providing a structured approach to quantify how thoroughly a design has been exercised. They complement directed tests with data-driven coverage analysis and support reporting in coverage reports produced by simulation tools.