cachememory

_cachememory_ is a small, high-speed storage that holds copies of data from frequently used main memory locations to reduce the processor’s average data access time. It leverages temporal and spatial locality to boost performance by keeping recently used values close to the CPU.

Caches are organized in several levels. L1 caches are the smallest and fastest, located on or near the CPU core. L2 caches are larger and slower, sometimes per-core, and L3 caches are even larger and may be shared among cores. Some systems also include an L4 cache. The hierarchy hides the latency difference between the CPU and main memory.

When the CPU requests data, the cache is checked for a matching block. If present, a cache hit returns the data quickly. If not, a cache miss occurs, and the block is fetched from the next memory level and stored in the cache, often evicting an existing block according to a replacement policy such as least recently used (LRU).

Caches can be direct-mapped, fully associative, or set-associative. Each cache line stores a data block plus a tag to identify the address. In multi-core systems, cache coherence becomes important, requiring protocols to maintain consistency across caches sharing data.

Write policy choices affect performance and correctness. Common policies include write-through (writes go to memory immediately) and write-back (writes are deferred until a dirty line is evicted). Coherence protocols like MESI help keep caches consistent.

The effectiveness of a cache is described by hit rate, hit time, and miss penalty. Average memory access time is influenced by these factors and by prefetching and spatial locality, which can improve hit rates. Cache memory is a central component of the memory hierarchy that significantly impacts overall system performance.