L1d

Level 1 Data cache, or L1D, is the smallest and fastest data cache in a modern CPU core. It stores data the processor has recently used or expects to reuse soon, reducing the latency of memory accesses compared with the Level 2 cache or main memory. L1D is typically separate from the Level 1 Instruction cache (L1I) and is private to each core, while higher caches may be shared or differently organized in various designs.

Typical organization and size: L1D sizes commonly range from 8 KB to 64 KB per core, with many designs in the 16–32 KB range. It is usually a few-way set-associative and uses cache lines of about 64 bytes. Latency is typically a few processor cycles (often around 4–6 cycles). The cache employs a write-back policy and write-allocate, meaning writes update the cache and are written back to memory later, and a write miss brings the corresponding line into the cache before writing.

Operation and data flow: On reads, the L1D is checked first; a hit delivers data to the core, while a miss fetches the data from L2 or higher in the memory hierarchy. On writes, data is updated in the L1D and eventually propagated to lower levels. Prefetchers may bring anticipated data into the L1D to improve hit rates and reduce stalls.

Role in performance and architecture: The L1D is a critical determinant of CPU throughput and latency, particularly for data-intensive workloads. It is typically private to each core, with L2 (and sometimes L3) caches serving larger, slower storage and providing coherence between cores. Design choices for L1D vary by microarchitecture, balancing speed, area, power, and security considerations.