CoreSightenabled

CoreSight-enabled describes devices such as microcontrollers or system-on-chip implementations that incorporate ARM's CoreSight debug and trace architecture. This enables hardware-assisted debugging, in-system programming, and trace data collection, facilitating efficient development, testing, and performance analysis.

CoreSight is a modular set of debug and trace components that can be integrated on silicon. Key elements include the Debug Access Port (DAP) which provides access from an external debugger via JTAG or Serial Wire Debug (SWD); and trace components such as the Trace Port Interface Unit (TPIU), Embedded Trace Macrocell (ETM), Instrumentation Trace Macrocell (ITM), Embedded Trace Buffer (ETB), and Serial Wire Output (SWO). Not all devices implement every component; some may include only debugging support without trace, or include trace with varying levels of depth.

The CoreSight architecture allows external debuggers to load firmware, set breakpoints, single-step execution, and observe registers. Trace features emit event information, instruction traces, and data traces that can be captured and analyzed by host tools. This can aid diagnosing hard faults, latency, and performance issues.

In practice, "CoreSight-enabled" is used in product briefs to indicate debug and trace capabilities are available. Access typically requires a compatible debugger probe and software; some features may require licenses or vendor-specific tools.

Important considerations include security and power; trace data may be disabled in production to protect IP or reduce overhead.