CMSISCORE

CMSISCore, also known as CMSIS-Core, is a component of the ARM Cortex Microcontroller Software Interface Standard (CMSIS) that provides a standardized, device-agnostic interface to the Cortex-M processor core and its peripherals. It defines the core register interface, enabling software to access features such as the Nested Vectored Interrupt Controller (NVIC), SysTick timer, Memory Protection Unit (MPU), Floating Point Unit (FPU), and core system registers (SCB, CPACR, CPUID) in a uniform way across Cortex-M devices.

CMSIS-Core supplies the device header files and startup code used to initialize the processor and set up the vector table, as well as the declarations and inline functions needed to access core registers and bit fields. It abstracts hardware differences between Cortex-M0/M0+, M3, M4, M7, and newer variants, facilitating code portability and reuse of low-level firmware, startup sequences, and debugging support.

The content typically includes language- and toolchain-compatible header files (for example, core_cm0.h, core_cm3.h, core_cm4.h, core_cm7.h), a CMSIS-CORE device header for a specific MCU device, startup assembly source, and the system_<Device>.c file that configures the system clock and memory settings. It also provides intrinsic helpers and macros for core register access and system initialization.

CMSIS-Core is intended for use by MCU vendors, middleware providers, and application developers to enable a common programming model across Cortex-M devices, complementing higher-level CMSIS components such as CMSIS-DSP and CMSIS-RTOS.