twtr

tWTR, or Write to Read Delay, is a DRAM timing parameter defined by JEDEC. It specifies the minimum interval between issuing a write command to a memory bank and issuing the subsequent read command to the same bank (or bank group). This delay helps ensure data integrity as the memory cell transitions from a write to a read state.

In practice, tWTR is measured in DRAM clock cycles and, at a given memory speed, can be expressed as a nanosecond value. In DDR4 and DDR5 memory, there are often separate constraints for reads following writes within the same bank group (tWTR_S) and for reads following writes across different bank groups (tWTR_L). The memory controller enforces the applicable constraint based on the specific sequence of commands.

tWTR affects both latency and throughput. Lower tWTR can reduce the waiting time before a read can occur after a write, potentially improving performance, but it may compromise stability if the memory or controller cannot safely recover. tWTR interacts with other timing parameters, such as tCAS (CAS latency), tRCD (row address to column address delay), tRP (row precharge), and tWR (write recovery time). Modern systems typically manage tWTR automatically through the memory controller and profile settings (for example, XMP), while manual tuning is mostly used by enthusiasts and overclockers.

Overall, tWTR is a key component of DRAM timing that helps balance speed and reliability, with its exact value varying by memory type, speed, and architecture.