Tflipflops

A T flip-flop, or toggle flip-flop, is a bistable circuit that stores a single bit and is controlled by a clock input. It has a data input T and outputs Q and Q' (the complement). On each active clock edge, the stored state updates according to T: if T is 1, Q toggles; if T is 0, Q remains unchanged.

In edge-triggered designs, the next state is Q_next = Q XOR T. Hence, when T = 0, Q_next = Q (no change); when T = 1, Q_next = not Q (a toggle). The same relation holds for Q'.

Implementations: A T flip-flop can be built from a JK flip-flop by wiring J = K = T, so the JK input toggles on clock edges when T is 1. It can also be realized with a D flip-flop by setting D = T XOR Q, so the D input encodes the toggle condition.

Timing and variants: Most common are edge-triggered types, often positive-edge triggered, with optional asynchronous preset and clear inputs. Negative-edge versions also exist. Level-sensitive T latches are possible but less common in synchronous designs.

Applications: T flip-flops are used to implement divide-by-2 counters and to build higher-bit counters by cascading stages. They serve as simple toggling elements in state machines and digital clocks, as well as in frequency division and timing circuits.