RSFlipFlop

The RS flip-flop, also known as an SR latch, is a basic bistable memory circuit that stores a single bit. It consists of two cross-coupled logic gates and has two inputs labeled S (set) and R (reset), along with two outputs, Q and Q̄ (the complement of Q). The device changes state in response to the inputs and holds its state when the inputs are inactive.

There are two common realizations. The NOR-based RS latch uses two cross-connected NOR gates. In this configuration, setting S to 1 and R to 0 drives Q to 1 and Q̄ to 0. If S is 0 and R is 1, Q becomes 0 and Q̄ becomes 1, resetting the latch. When both S and R are 0, the latch holds its previous state. When both inputs are 1, both outputs become 0, which is an invalid/undefined condition for the NOR implementation.

The NAND-based RS latch uses two cross-connected NAND gates and active-low inputs, often labeled S̄ and R̄. With S̄ = 0 and R̄ = 1, the latch sets, yielding Q = 1 and Q̄ = 0. With S̄ = 1 and R̄ = 0, the latch resets, yielding Q = 0 and Q̄ = 1. When both inputs are 1, the latch holds its state. When both inputs are 0, both outputs become 1, which is the invalid condition for the NAND implementation.

RS flip-flops are asynchronous memory elements and are level-sensitive; they respond directly to input levels rather than clock edges. To create an edge-triggered flip-flop, gating arrangements (such as a master-slave configuration) are used to convert the latch into a true RS flip-flop. Applications include simple memory storage, synchronization primitives, and foundational building blocks in more complex sequential circuits.