Cacheblok

Cacheblok, in computer architecture often referred to as a cache block or cache line, is the unit of data stored and transferred between a cache and its next memory level, such as the L1 or L2 cache. A cacheblok represents a fixed-sized chunk of memory and includes both the data payload and metadata used to manage the cache.

The block size is fixed by the cache design and typically ranges from a few dozen to a couple hundred bytes (for example, 32, 64 or 128 bytes). Each block carries a tag that identifies the corresponding block in main memory, a valid bit to indicate whether the data is usable, and often a dirty bit in write-back caches to mark whether the block has been modified. In multi-level caches, coherence states (such as those used in MESI) may also be tracked at the block level.

When the processor accesses memory, the cache checks the relevant cache set for a block whose tag matches the address. If a matching and valid block is found, a cache hit returns the data quickly. If not, a cache miss occurs, and the block is fetched from a lower level of memory (or from memory proper), possibly replacing an existing block according to a replacement policy such as LRU or FIFO.

Block size influences performance: larger blocks improve spatial locality and reduce miss rate for sequential access but can increase cache pollution and bandwidth consumption. The cacheblok concept is closely related to the general idea of a cache line, varying terminology by language and architecture documentation.