ALUSrc

ALUSrc is a control signal used in the CPU datapath to determine the second operand fed to the arithmetic logic unit (ALU). In many MIPS-style single-cycle designs, ALUSrc is implemented as a one-bit multiplexer that selects between the second register operand and a sign-extended immediate value derived from the instruction.

When ALUSrc is 0, the ALU’s second input comes from ReadData2 (the second register file output). This configuration is used for R-type instructions that operate on two registers, such as add, sub, and, or, and slt. When ALUSrc is 1, the ALU’s second input comes from the sign-extended immediate field, enabling I-type instructions such as addi, lw, and sw to perform operations with an immediate operand.

In the standard MIPS datapath, ALUSrc works in concert with other control signals that determine the ALU operation (via the ALU control unit) and with mechanisms that compute branch targets. For beq and similar branches, ALUSrc is typically 0 so the ALU can compare two registers via subtraction; the branch offset is computed using the sign-extended immediate (shifted left by 2) in a separate adder.

In summary, ALUSrc is a key, single-bit control that selects between a register-based operand and a sign-extended immediate as the second input to the ALU, enabling the CPU to handle both register-type and immediate-type instructions efficiently.