memorycoherence

Memory coherence is a property of a shared-memory multiprocessor system that ensures memory reads and writes to the same location appear in a consistent order across all processors. In a coherently managed system, a read of a memory location returns the most recently written value by any processor, according to the rules of the active cache-coherence protocol. Coherence is related to, but distinct from, memory consistency models, which define allowed orders of memory operations; coherence focuses on the visibility of updates to a single location across caches.

Cache coherence is typically implemented by protocols that track the state of each cache line and coordinate actions among caches. The main approaches are snooping protocols, suitable for bus-based or smaller-scale systems, and directory-based protocols, which scale better for larger multiprocessors by tracking where copies of a line exist. Common protocols include MSI (Modified, Shared, Invalid), MESI (Modified, Exclusive, Shared, Invalid), and more advanced variants such as MOESI (Modified, Owned, Exclusive, Shared, Invalid) and MESIF (Modified, Exclusive, Shared, Invalid, Forward). These protocols define state transitions and dictate whether a line must be invalidated or supplied from another cache on reads and writes, thereby maintaining a coherent view of memory.

Performance considerations include coherence traffic, latency, and phenomena such as false sharing, where independent data stored in the same cache line cause unnecessary invalidations. In multicore and many-core systems, memory fences or barriers are often required to enforce ordering constraints beyond what coherence guarantees. Understanding coherence is essential for designing scalable systems and for reasoning about data races and synchronization.

See also memory consistency model, cache coherence protocol, directory-based coherence, snooping, and false sharing.