GAAFET

Gate-All-Around Field-Effect Transistor (GAAFET) is a transistor architecture in which the gate electrode wraps around the conducting channel on all sides. This geometry provides superior electrostatic control of the channel compared with planar or FinFET structures, enabling better suppression of short-channel effects and improved current drive for continued device scaling. The channel is typically formed from a nanoscale semiconductor such as silicon and can take the form of a nanowire or a nanosheet, with either a single channel or multiple stacked channels to increase current capability.

Fabrication uses a gate dielectric and metal gate that surround the channel. In nanosheet implementations, several ultra-thin silicon sheets are laid in parallel beneath a common wraparound gate. In nanowire variants, a slender nanowire serves as the channel. Doping strategies vary; some GAAFET designs rely on undoped, fully depleted channels, while still enabling conventional source/drain junctions.

GAAFETs offer improved gate control, higher drive current per footprint, and reduced leakage compared with FinFETs, supporting continued scaling to smaller nodes. They are considered a leading technology option for future CMOS nodes and have been the subject of research and limited production pilots by major semiconductor foundries during the 2010s and 2020s.

Challenges include complex three-dimensional lithography, deposition, and etching of nanoscale structures, variations in nanosheet or nanowire dimensions, and integration with existing manufacturing steps. Realizing reliable high-volume production requires advances across process control, materials, and design methodologies.