DIBL

Drain-induced barrier lowering (DIBL) is a short-channel effect observed in metal-oxide-semiconductor field-effect transistors (MOSFETs) where the drain electric field lowers the potential barrier at the source-channel junction. As a result, the threshold voltage decreases with increasing drain-to-source voltage (VDS), and the device can conduct more when it should be off. DIBL is commonly quantified as DIBL = ΔVth / ΔVDS, where ΔVth is the change in threshold voltage for a given change in VDS, typically expressed in millivolts per volt (mV/V).

Mechanism and impact. In short-channel devices, the drain field extends into the channel, perturbing the electrostatic potential near the source end. This reduces the barrier for carriers to inject from the source, effectively lowering the gate voltage needed to turn the device on and increasing off-state leakage. DIBL also affects the subthreshold behavior, narrowing the switching slope and degrading immunity to drain-induced leakage.

Factors and device scaling. The magnitude of DIBL increases as channel length decreases and is influenced by doping profiles, oxide thickness, gate work function, and temperature. Higher drain voltages and aggressive scaling typically exacerbate DIBL. It is observed in both NMOS and PMOS devices, though often more pronounced in NMOS structures.

Mitigation and modelling. Techniques to reduce DIBL include multi-gate architectures (such as FinFETs and trigate transistors), improved gate control with high-k/metal gate stacks, lightly doped drain regions, halo implants, and optimized device geometry. DIBL is an important parameter in compact transistor models (for example BSIM models) and is used to predict short-channel behavior and leakage currents in circuit design.

In summary, DIBL describes the drain-driven lowering of the source-barrier in short-channel MOSFETs, influencing threshold voltage, leakage, and overall device performance as transistor dimensions shrink.